Abstract In this short

Abstract

In this short, based on the physical mechanism together with a reasonable transistor size, a robust 10T memory cell is the first proposed to improve the level of reliability in the environment of aerospace radiation, maintaining the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company Standard commercial process of 65 nm CMOS, simulations performed in Tanner tool demonstrate the capacity of the proposal 10T cell hardened by radiation to tolerate both 0 to 1 And 1 to 0 upsets with single node, with both read / write operations can be accessed.

INTRODUCTION
SRAMs have been widely adopted in various aerospace electronic systems, and play an important role in the delay, area, power and criticality Reliability In aerospace applications, SRAMs have a fundamental limit this constitutes a challenge in the reliability induced by energy particles. Therefore, disturbed individual events (SEUs) represent a serious reliability error mechanism that can cause a malfunction of an electronic system override the stored value. When the load the particle hits a sensitive node of an integrated circuit, the charge along its path can be collected and accumulated efficiently through drift processes. Once a transient voltage pulse is generated of the accumulated load is above the switching threshold of the circuit, the value stored in this sensitive node will be changed.
However, it is the fact that the SRAM cell which is of 6T is usually built using two cross coupling inverters and the value modified in a stored node can also activate the positive feedback mechanism to flip the state to another sensitive node so that an error occurs in memory Because this corrupt information can be completely recovered from overwriting operations, this phenomenon is also reported as soft errors.
In general, with the resizing of the CMOS process technology, the SRAM cells are more vulnerable to this reliability challenge due to the increase density, reduction of critical load and reduction of supply voltage. Therefore, the robustness of the soft error with the hardened radiation Design techniques (RHBD) are an increasingly important prerequisite in aerospace applications for the reasons described above and cosmic radiation environment more complex and proposing is the new high efficiency and high reliability RHBD memory cell it is necessary.
Recently, there are many remarkable radiations hardened by design cell studies had been reported based on circuit level redundancy or redesigning a memory cell to provide fault tolerable capability. For example, the RHBD memory cells like PS-10T and NS-10T memory cells which use stacked structure. The defect of the design that it can provide only one SEU robustness that is NS-10T cell provide 0 to 1 SEU instead of 1 to 0, whereas PS-10T cell has the ability to tolerate both 0 to 1 and 1 to 0 SEUs but incapable of doing action. An RHBD Quatro-10T memory cell has proposed to reduce only 1 to 0 SEU by relying on a negative feedback.
In a RHBD 11T memory cell, this still stores value by blocking the feedback path to prevent the induced transient impulse that affects the next nodes. Nevertheless, for this RHBD 11T memory cell, due to the single-ended structure, differential writing and reading capabilities are not enabled, which may increase the operating time. In a DICE memory cell, it is proposed using 12 transistors, which uses two interlocked latch pair to store the complementary values so that the effected values can be recovered to its original value using positive feedbacks. Redesigning a cell structure and using a shallow trench insulation technique, a RHBD 12T memory cell is proposed at the cost of large area above the head. However, the common disadvantage of 11T, Dice and 12T cells indicate that their general areas are larger. Hence, all the previous RHBD cells are not suitable for aerospace applications in which the RHBD memory cells with efficient area and high reliability properties are necessary to offer appropriate designs reliability systems
In order to solve this contradiction, a novel area-efficient, low-power, and high-reliability RHBD 10T memory cell is proposed using a circuit-level hardening technique. According to SEU physical theory together with reasonable transistor size, it can provide high radiation hardening capability at the cost of write and read access times. Intuitively, this brief is mainly organized as follows.

Theoretical Analysis:

Schematic of RHBD 10T memory cell

Operation Analysis:
For the proposed RHBD 10T memory cell, Fig describes its basic schematic structure. From this figure, it can be seen that the proposed RHBD memory cell consists of ten transistors in which PMOS transistors are transistors P1 ~ P6, and the remaining transistors (N1 ~ N4) are NMOS transistors. Both NMOS transistors N4 and N3 are defined as the access transistors, and their gates are connected with a word line (WL). Hence, when this WL is in high mode (WL = 1), two access transistors are turned ON. At the moment,
Write/read operation can be implemented. The stored nodes are nodes Q, QN, S1, and S0 in which these four nodes are responsible for keeping the stored value correctly. In order to quickly transmit the digital signal to the output port during a read operation, a differential
Sense amplifier has to be employed and connected with two bit lines BL and BLN.
Assuming the stored value of the RHBD 10T proposal the memory cell is 1 in digital logic, that is, Q = 1, QN = 0, S1 = 1, and S0 = 0, as shown in Fig. We can easily imagine it
The proposed 10H RHBD memory cell maintains memory continuous value when the WL is driven by a low voltage (WL = 0). Before normal read the operation, due to the preload circuits, of the bit line voltages BL and BLN will be brought to 1 in digital logic. In the reading operation, WL is in high mode (WL = 1), so two access transistors N3 and N4 are switched on immediately. Nodes Q, QN, S1 and S0 saves the stored value and the bit line voltage BL is not modified However, the BLN network voltage is reduced due to the discharge operation through the transistors ON N1 and N3. Once the voltage difference of bit lines is a constant value which has been confirmed in the differential sense amplifier connecting with two bit lines, the stored digital signal in memory cell will be output as soon as possible. The purpose of write operation is to change the stored logical value correctly. Therefore, before write operation, due to the write circuitry, the voltages of bit line BL will be 0 in digital logic. Contrary to the voltage of bit line BL, the voltage of bit line BLN will be 1. When the voltage of WL is supply voltage VDD (WL = 1), write operation is executed. Transistors N2, P2, P3, and P6 are turned ON. At the moment, the states of transistors N1, P1, P4 and P5 will be OFF, so that the logical value of this memory cell is rightly changed to 0. Therefore, write operation can also be completed successfully.

SEU Recovery analysis:
Let us consider the stored 1 state again, as shown in Fig. For the RHBD 10T memory cell, according to SEU physical mechanism, nodes Q, QN, and S0 are three sensitive nodes for this stored value.
• If the sensitive node Q is flipped to state 0 by a charged particle, transistor N1 will be temporarily OFF, and the switch state of transistor P6 will be ON temporarily. However, the voltage of node S1 will be its initial state, because the size of transistor P1 is larger than that of transistor P6 (2.1× larger). As a result, the voltage of node S0 is unchanged. Hence, transistor P4 will be always ON. Finally, the voltage of node Q will be flipped to the initial voltage.
• If the sensitive node S0 is induced to change the initial state by a radiation particle, both transistors P1 and P4 will be temporarily turned OFF, and the nodes Q, QN, and S1 will be unchanged due to capacitive effect. Therefore, transistor P5 will be always ON, and the voltage of node S0 will be restored.
• When node QN is flipped, the switch states of transistors N2 and P5 will be temporarily turned ON and OFF, respectively, and then the voltage of node Q will be changed to 0 state. Hence, transistors P6 and N1 will be also temporarily turned ON and OFF, respectively. However, due to the larger size of transistor P1, the value of node S1 will be its initial value so that transistor P2 also remains its OFF state. Therefore, the affected node Q will be pulled up to 1 state, and then transistor N1 will
be turned ON again, and node QN will be pulled down to 0 state.